Contamination mitigation of hydrogen silsesquioxane resist processed with Na+-containing developer for nanoscale CMOS device patterning

Abstract

Research on continued complementary metal–oxide–semiconductor (CMOS) scaling has sparked an interest in fabricating silicon-based devices with features in the sub-30 nm pitch regime. Electron beam lithography using hydrogen silsesquioxane (HSQ) resist processed with developers that contain ionic salts, e.g., Na+, has demonstrated a way to cleanly pattern features in the 20–30 nm pitch regime. Contamination concerns, however, have prevented the application of salty developed HSQ to silicon CMOS device integration in laboratories with stringent contamination controls. This paper details the results of a study aimed at understanding and reducing the residual contamination of salty developer to a level suitable for continued processing in a CMOS device research line. Data from total reflection x-ray fluorescence measurements shows that significant levels of Na+ as well as other unexpected metal contaminants remain on substrates after the develop process. Capacitance versus voltage measurements of capacitor structures were used to demonstrate that the Na+ contamination can be removed through a rigorous rinsing protocol. However, the metal contaminants proved harder to eliminate and required formulation of the developer solution using high purity constituent components. Using these protocols, integrated FinFET capacitors with a minimum Silicon fin pitch of 30 nm were successfully fabricated. The data from these devices show nominal device characteristics with no indication of ionic or metal contamination.