Abstract
With the advent of 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating dies of various functions. However, due to the instability in the TSV fabrication process, various types of failure can be resulted, resulting in drastic decrease in the final chip yield with the increase in the number of TSVs and stacked dies. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure that can detect TSV defects on wafer-level, while overcoming the limitations of the conventional direct probing method. TSVs are aligned and connected as to enable the detection of change in the series capacitance between adjacent TSVs for verification of the TSV defects. Through time- and frequency-domain simulation results, we verified that the proposed structure can successfully detect TSV defects.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
