Contact Etch Schemes at Advanced Logic Technology Nodes

Abstract

Since CMOS technology moved to sub40nm node and beyond, the limits of both pre-etch and post-etch process have posed the huge challenges to contact etch itself, contact etch is playing a more and more critical role in yield enhancement. In this paper, we addressed the different schemes for both gate-first process and gate-last process to deal with the limits of pre-etch conditions including the ILD (inter-layer dielectrics) thick variation related litho local defocus, the random photo resist footing/scumming, the much thinner ILD thickness on gate, the excessively small pitch related overlay effect and the impact of gate height, and to handle the limits of post-etch processes such as WET clean related polymer remaining and W gap-fill related W missing. In brief, besides the well optimized traditional etch processes to deliver the vertical contact hole, both the pre-etch treatment and the special flush step are indispensable to broaden the overall contact loop process window, reduce the contact open and/or high Rc issue. Both indexes are highly related to final yield performance.