Abstract
Contact level is the first metal (usually tungsten) connection level between the device and the aluminum or copper interconnects. Depending on the device type (CMOS, memories, photonic device) and technology node, contact patterning is in constant development to improve performance. At the contact cleaning step, we face many new challenges due to the metal or sensitive material exposure with the cleaning chemistry, the decrease of nominal dimensions and the increase of aspect ratio. In particular, new contact clean processes were developed for CMOS devices (28nm and 14nm nodes), and photonic devices, in order to be compatible with metal gate or germanium photodiode.In this study, we will compare the efficiency of these new cleaning processes with standard contact clean previously used for CMOS devices from 90nm down to 45nm nodes. We will also highlight cleaning efficiency in high aspect ratio structures, and optimized IPA drying capability on a single wafer cleaning tool.
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