Construction of up‐down‐type and shift‐register‐type counters using ternary flip‐flop circuits

Abstract

AbstractConstruction methods for ternary logic circuits and ternary tri‐stable flip‐flops, using ternary basic operational circuits composed only of CMOS‐ICs have been reported. This paper discusses the construction methods for ternary sequential circuits, such as ternary counters, using those ternary logic circuits and ternary tri‐stable flip‐flops. Among various types of ternary tri‐stable flip‐flops, this paper uses two‐stage ternary up, down and up‐down type JK flip‐flops. As the logical‐type ternary counters, up, down and up‐down type divide‐by‐10 counters are realized. Considering then, the constructions of divide‐by‐2 to 9 counters, the input equations for the ternary up‐ and down‐type JK flip‐flops are determined. The feedback‐type ternary divide‐by‐8 counter is also discussed. As the ternary shift‐register type counters, ternary ring counter, ternary Johnson counter, clockwise and counter‐clockwise cycling counters are realized.