Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator

Abstract

The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tail comparator is 0.38035 followed by the dynamic comparator is 0.4934. Insignificance of 0.150 was obtained which is greater than (p<0.05). Conclusion: The consumption of power by the constructed CMOS logic double tail comparator appears to be less than dynamic double tail comparator.