Constraint Analysis for DSP Code Generation

Abstract

This chapter focuses on the problems of register binding and scheduling under timing constraints. Digital signal-processing design groups and embedded processor users indicate the increasing use of application-domain-specific instruction-set processors (ASIPs) as a significant trend. Application-specific instruction-set processors (ASIPs) are tuned toward specific application domains and have become popular due to their advantageous tradeoff between flexibility and cost. This tradeoff is present neither in application-specific integrated circuit (ASIC) design, where emphasis is placed on cost, nor in the design of general-purpose digital signal processors (DSPs), where emphasis is placed on flexibility. Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by hardware architecture. The analysis identifies implicit sequencing relations between operations in addition to the preceding constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints.