Design of PIONEER: A case study using NoGap

Abstract

Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. The flexibility of ASIPs makes them preferable over fixed function Application Specific Integrated Circuits (ASICs). Also, a well designed ASIP, has a power consumption comparable to ASICs. However the cost associated with ASlP design is a limiting factor for a more wide spread adoption. A number of different tools have been proposed, promising to ease this design process. However all of the current state of the art tools limits the designer due to a template based design process. We have therefore proposed the Novel Genrator of Accelerators And Processors (NoGap). NoGap is a design automation tool for ASIP design that puts very few limits on the designer, yet it supports a designer by automating much of the tedious and error prone tasks associated with ASIP design. This paper presents a case study, where we have used NoGap to design a Reduced Instruction Set Computing (RISC) processor, with DSP extensions, which we named PIONEER. The NoGap generated System Verilog code was synthesized using both an FPGA and ASIC flow. With no FPGA specific optimizations, PIONEER meet timing closure at 203 MHz in a Virtex-4 LX80 speed grade 12. PIONEER was successfully tested in an FPGA by running some typical Digital Signal Processor (DSP) application such as Finite Impulse Response (FIR) filters, and a Discrete Cosine Transform (DCT). area and power consumption of the ASIC design was 24815 μm2 and 1.607 mW (estimated) respectively. Time closure where met at 300 MHz. Examining the critical paths we could conclude that hardware synthesized by NoGap was not a limiting factor.