Abstract
A synchronous binary counter is one of the basic components widely used in VLSI design, and it is required to be fast and support a wide bit-width in many applications. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. This brief proposes a new fast structure for synchronous binary counting, which has a minimal counting period for practical counter sizes ranging from 8 to 128 bits. We first adopt an 1-bit Johnson counter to reduce the overall hardware complexity, and then duplicate the 1-bit Johnson counter to decrease the propagation delay caused by large fan-outs. Implementation results show that the proposed design can be realized with a small number of flip-flops, which is almost linear to the counter size, and it operates at a clock frequency of 2GHz in a 65nm CMOS technology, being limited only by the counting rate of the least significant bit.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
