Constant hardware delay in integrated switching elements with multiserver output queues

Abstract

The authors consider an integrated switching element with a shared buffer memory and a constant hardware delay. This hardware delay is caused by the hardware operations required to process the routing information of incoming cells. A general uncorrelated cell arrival process in the switch, an independent and uniform routing process of cells from the inlets to the outlets of the switch and a first-come-first-served queueing discipline are assumed. The performance of the switching element is evaluated by means of an analytical technique based on an extensive use of probability generating functions. Explicit expressions for the probability generating functions, the mean values, the variances and the tail probabilities of the occupancy and the cell delay of the switch are obtained. Numerical examples show that the hardware delay has an important impact on the switch performance.