Dimensioning of shared buffer ATM switch elements

Abstract

ATM communication systems have introduced a number of new dimensioning problems, one being the evaluation of the loss probability for a shared buffer memory within a switch matrix. This is a problem of growing interest since shared buffer memory switches offer the best cell loss probability versus total buffer space provided, and thus are often the design of choice. ATM switches operate in a time slotted fashion: at the end of each slot, N cells will have been transmitted if all N servers have cells for transmission. If a server has no cell to transmit, it will produce an empty slot. Iliadis (1991) has presented a method for solving such a system based on the introduction of an N dimensional Markov chain. Schormans et al. (see Electronics Letters, vol.30, no.1, 1994) have presented a simplified algorithm for a fairly general arrival process. This paper considers certain problems in (shared) buffer dimensioning: calculation of the cell loss probability (CLP) for a 2/spl times/2 switching element, given any i/p loading; the effect, on such a shared buffer switching element, of allowing the applied traffic to approach the limit, i.e. during each time slot every input line will contain a new cell; and the relationship between the cell loss probability and the model of the routing strategy.