Considerations of performance factors in CMOS designs

Abstract

Recently, designers have been using the energy-delay product (EDP) as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product (PDP). As the industry moves to deep sub-micron technology, it is appropriate to investigate existing design metrics. In this work, we investigated the performance metrics, and generalized set of metrics are proposed. Supply voltage (VDD) and threshold voltage (VT) scaling are two popular approaches to power reduction. We analyzed their effects on power and frequency and search for feasible region of operation. The relationship between the optimal operating points and generalized design metrics is established. We present some new insights in power considerations of deep submicron CMOS designs. We compared EDP with PDP and introduced a new metric called power-energy product (PEP). Comparing the three metrics, it is observed that EDP places a higher weight on delay reduction, PEP places a higher weight on power reduction, and PDP tries to strike a balance between the two.