Congestion mitigation using flexible router architecture for Network-on-Chip

Abstract

An important topic in Network-on-Chip (NoC) design is the tradeoff between area and performance. Some techniques tend to increase the number of buffers to improve performance. However this method increases the chip area and so does the power consumption. In this paper we introduce a new flexible router architecture that can improve the performance of the overall network using the same amount of buffering available but in an efficient way. Therefore there is no need to increase the size of buffers or to use extra virtual channels (VCs) which have high power and area overheads or complex logic. If there is a request to a busy buffer the router will store the incoming packet in any other suitable free buffer in the router. The Flexible router shows an increase in performance in terms of increasing the saturation rate for Hotspot, Uniform, and Nearest-Neighbor traffics, especially Hotspot with 11.4% increase. Discussion about area overhead over a standard Base router and the analysis of arriving unordered packets (side-effect) are also presented.