Configuring a boundary scan chain for optimal testing of non-scan logic clusters

Abstract

Testing of boards containing a mixture of boundary scan components and clusters of non-boundary scan logic is an interesting problem. If a tester cannot contact the non-scan logic clusters, the inputs and outputs of on board boundary scan devices may be used as virtual access points to test the clusters. In that case, the time required for testing the clusters depends on how the boundary scan chips are connected into a longer scan chain. This paper presents a technique for configuring a chain of boundary scan chips to minimize the test time for nonscan logic clusters.