Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis

Abstract

Three-dimensional integration is a key technology for systems whose performance / power requirements cannot be achieved by traditional silicon technologies. Testing is one of the major challenges of 3D integration. This paper proposes a configurable Interconnect Built-In Self-Test (BIST) technique for inter-die interconnects (Thru-Silicon Vias TSVs). The proposed technique accounts for faults like opens and shorts and also delay faults due to crosstalk. In the proposed fault model, the signal transitions on victim TSVs are affected by the transitions on the aggressor TSVs. The Kth Aggressor Fault model (KAF) assumes that the aggressors of each victim TSV are the K-order neighbors. The test times are reduced as more victim TSVs are concurrently tested. The neighboring order K is technology dependent and it is determined such that the test times are minimal without loss in fault coverage. The proposed BIST has lower area than existing interconnect BIST solutions, while the configuration capabilities increase the area by up to 80%. However, due to relative high TSV pitch (10s μm), the area overheads are small.