Abstract
Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we propose in this article a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. We exploit different memory tiling configurations to reduce the memory area about 20%. The proposed architecture was synthesized for a 90 nm process design with a variable number of processor nodes and a competitive circuit area of 6.2 mm2 was achieved. The operating frequency simultaneously guarantees throughputs superior to 90 Mbps, as required by DVB-S2, and low levels of power consumption.
Highlights
Over the last 15 years Low-Density Parity-Check (LDPC) codes have assumed a growing importance in the channel coding arena, namely because they have error correction capability to achieve efficient coding close to the Shannon limit
In this article we tackle these challenges, namely by materializing the benefits and quantifying the gains achieved with the Very Large Scale Integration (VLSI) design of this architecture, in particular regarding the complex design of Application Specific Integrated Circuit (ASIC) memory blocks that can benefit from the use of the reduced number of processors
We present synthesis results for a memory optimized ASIC architecture that compare well with those reported in state-of-the-art solutions of Digital Video Broadcasting-Satellite 2 (DVB-S2) LDPC decoders [5,6,7,15,16]
Summary
Over the last 15 years Low-Density Parity-Check (LDPC) codes have assumed a growing importance in the channel coding arena, namely because they have error correction capability to achieve efficient coding close to the Shannon limit. We have reduced significantly the routing complexity of the interconnection network between processor nodes and memory blocks, which represents a target that aims to improve the design in terms of cost and complexity This architecture has been initially proposed in [14], but some important challenges have not been addressed yet. The main contributions of the article are: (i) efficient, scalable and parallel architectures with any submultiple of M = 360 number of processors for VLSI-based LDPC decoders under the context of DVB-S2; (ii) optimized synthesis area results for different sets of functional units and corresponding memory blocks reconfiguration; (iii) architecture with reduced routing complexity, occupying small die areas and consuming low power; and (iv) decoders with high throughput
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