Concurrent Test Implementations

Abstract

Today's large SOC devices include many different IP blocks which tested sequentially add significant test time to the production flow. Testing of several devices in parallel is one way to reduce test time and cost per device. However, as more functionality is added to the SOCs, the pin count will increase and limit the number of sites that can be tested in parallel. One method to reduce test time per device is to concurrently test multiple areas of the device at the one time. Concurrent test is a methodology to test various sections of the device in parallel. This paper will discuss three different types of concurrent test. The first type of concurrent test takes advantage of the ATE's per pin electronics to perform DC or frequency measure tests in parallel. One example is running several PLL clock tests at once. A second type of concurrent test makes use of the device's DFT modes to execute simultaneous tests on different IP blocks. An example of this is executing time consuming digital tests like scan concurrently with analog tests like RF tuners or serial ATA. A third method to reduce test time is to start a new test while the previous results are still being calculated. Processing captured data can be done at the same time other tests are being executed. This could be applied to the outputs of ADCs or DACs where large amounts of data are processed by one or more embedded processors in the ATE while subsequent tests are running. Some of these techniques require the implementation of DFT at design time to allow multiple blocks to function simultaneously and independently of each other. The test board must also be designed with careful consideration to concurrent test. The ATE will play a key role in that it must support concurrent test features in its hardware and software. Implementing concurrent test will result in higher throughput and lower test cost which every semiconductor company must obtain to stay competitive.