Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation

Abstract

In this work, we present extensions to the SystemC library and automatable model transformations that enable efficient system-level fault simulation in SystemC. The method is based on extended data types which represent variables or signals as lists of values (instead of one value) consisting of a fault free reference value and any number of faulty values each of which corresponds to one fault. We inject faults (variable level faults as well as bit level faults) into objects declared with the extended data types. These faults are then propagated to other objects during SystemC simulation, until either they are classified and dropped or the simulation ends. The extended SystemC simulator is intended for robustness evaluation of digital and embedded designs, for which we propose a condition-oriented quantitative fault model. Speedups of up to 1905 and 10 are achieved for transient faults in digital circuit simulation and for a custom fault model in software algorithm robustness evaluation, respectively.