Computing for Diagnosis of HDL Code

Abstract

This chapter describes a structural method for system-on-a-chip (SoC) Hardware Description Language (HDL) model diagnosis, based on redundancy, called a Transaction-Level Test Assertion Blocks Activated Graph (TABA graph). The structural method of faulty block diagnosis is aimed at decreasing the time needed for detection of faulty HDL blocks and the memory needed for storage of a Test Assertion Blocks Activated Matrix (TABA matrix) in the hardware design. The objects are solved: creation of an HDL assertion-based transaction-level graph and fault detection table of HDL blocks, as a matrix for activation of the functional HDL components by leveraging the selected assertions and test patterns; creation of diagnosability metrics for evaluation of an assertion-driven HDL diagnosis model; and development of a method for assertion-driven analysis of the activation matrix to diagnose errors in blocks with the given depth of the HDL code. The developed structures and method for assertion-driven diagnosis are implemented in the design verification software tools.