Abstract
Physical mechanism of gate-lag or slow current transient in GaAs MESFETs is studied by two-dimensional simulation including surface-state effects. It is shown that the gate-lag becomes noticeable when the deep-acceptor-like surface state acts as a hole trap. To reduce it, the deep acceptor should be made electron-trap-like, which could be realized by reducing the surface-state density. Structures expected to have less gate-lag, such as a self-aligned structure and a recessed-gate structure are also analyzed. It is discussed whether the gate-lag can be completely eliminated in these structures.
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