Abstract
The article presents a block diagram of the improved algorithm and computation module accelerated division by neurons. Scheme is proposed to use a computing device " divider neurons " containing block divider register, proposing to extend additional functionality computing and control blocks: a data input unit used to load calculated values, the register block of the dividend, which is a set of registers for storing information used in the transaction value unit amounts and forming discharges private unit overload analyzer digit grid, overflow stop computing managing, register residue private block. The resulting device can be used for the synthesis of arithmetic logic units, to create a high-speed and high-speed digital systems, and able to increase reliability of the computing hardware module that uses the division operation on the basis of number of neural module.
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