Abstract
This paper is concerned with the automatic generation of multi-row schematics. The characteristics of those schematics and the conditions to be met in the layout process are examined in detail. All stages of the generation cycle including data entry, partitioning, placement, and routing are considered. Brief descriptions of the main algorithms are given. A graph theoretic approach to the preplacement of the components is presented having some interesting applications to matrix theory. The physical placement aims at supporting the aesthetics of the drawing. A modified channel router is used to draw the interconnections between the symbols of the schematics. At present the algorithms are implemented to generate logic schematics.
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