Computer aided electron beam testing for VLSI circuit analysis

Abstract

The program embarked upon aims at providing an integrated debug system for production devices which will reduce the time, effort and skill level required to identify fault locations on VLSI devices. This paper discusses some of the methods employed in attempting to realise this objective. Computer control is widely used in order to speed up the set-up of system parameters and minimise the amount of 'expertise' required to operate the system. Workstation utilities are used in order to simplify the user interface by standardising all system operating procedures to one format. Two image comparison methods are detailed. The first utilises the subtraction approach widely reported for global picture interpretation. The second is a more efficient technique enabling a logic state table of specified conductors to be created and compared for a reference device and a device under test. Finally, a technique utilising video gating together with capacitive coupling voltage contrast is detailed for successfully acquiring dynamic voltage contast images of conductors under layers of passivation. The present limitations of this system and future perspectives for improvement are also highlighted.