Abstract

Computational optimization through approximation approach proves to be an effective way for Digital Signal Processing (DSP) at anemometric scales. Here approximation methodology is discussed to design arithmetic blocks of DSP. Implementation on Xilinx ISE 13.2 on Spartan 6 is done for approximate arithmetic block analysis like adder and multiplier which are capable to do area, power and delay optimization if some error is tolerable. Approximate Computational Complexity (ACC) method based 4:2 compressor is designed for image compression gives area, delay and power reduction as 18%, 7% and 49% respectively. Area and power optimized 8 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">*</sup> 8 image compression obtained at the cost of 20% increase in error rate which is tolerable with reference to adequate PSNR.

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