Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding

Abstract

In applications such as digital signal processing and machine learning, the accuracy of internal operations is not so strict due to the limitation of human perception. Approximate computing has been focused as an effective way to trade off energy against accuracy. In this paper, a new type of approximate floating-point (FP) multiplier is proposed by applying radix-8 Booth encoding to the mantissa part. We devise the addition of the triple of multiplicand in radix-8 Booth encoding. Experimental results show the proposed design can achieve significant reduction in area, delay and power up to 66.48%, 23.39% and 69.02% while losing only 0.18% accuracy when compared with the IEEE-754 single precision FP multiplier. The proposed multipliers are applied to image smoothing and image compression and show negligible quality loss.