Computational Simulation of Square using Low Power Vedic Algorithm and its Implementation on FPGA

Abstract

The project’s main goal is to create Vedic Square Technologies for different applications based on historical Indian Vedic Mathematics Sutras. Modern computing equipment has an insatiable desire for quick calculation. The main computational units are adders and multipliers. So far, various sorts of multiplier structures have been proposed to speed up product computation. We must lower the system’s lag for any function. In comparison to standard multiplier designs, Vedic mathematics offers mathematical ways to enhance speed and lower power usage. The Urdhava Tiryakbhyam Sutra approach and also the Carry Select Adder methodology are beneficial for reducing power consumption in Vedic multiplication algorithms. UTM stands for Vedic mathematics that is applied vertically and crosswise. Low speed and leakage power have been common problems in circuit design. In comparison to previous algorithms, our proposed multiplication algorithm has a shorter time delay. Power Saving Vedic Square architecture is discussed in this study. The power consumption of these Vedic multiplier systems is reduced, and the outputs are generated faster [1]. We have done the following analysis: - a) Frequency Analysis, b) Effect of Output Load variation on Power Consumption, c) Effect of I/O Toggle Rate variation on Power Consumption, d) Voltage Scaling Analysis, e) Power Analysis on different development boards. Using Xilinx ISE Design Suite 14.7, the approach is programmed using Verilog HDL, and then obtained the simulated timing diagram after synthesizing. The design was implemented on Xilinx Artix-7 (XC7A200T).