Compression and packetization for MPEG-2/4 video and audio

Abstract

We describe a flexible LSI architectural design concept suitable for various video-oriented multimedia applications. Our proposed LSI design assumes various schemes and picture formats of compression in a single-chip architecture. The hybrid architecture of an high-performed embedded Digital Signal Processor (DSP) core and dedicated hardware processing units, and its scaleable architecture are the key features. DSP core supports the processing that requires the complexity and flexibility and lower processing power. Hardware parts support the processing components that are frequently used and require processing power and lower complexity. In this architecture, evaluated performance shows that a single chip can perform MPEG MP@ML (Main Profile at Main Level) processing including video and audio codec, and media packetization. With its scaleable architecture, MPEG MP@HL (Main Profile at High Level) compression can be carried out with only 6 chips. This single LSI can also have a capability of extending to H.263 or forthcoming MPEG-4 standard algorithm by a single chip on the embedded DSP core basis.