A low-power digital signal processor core by minimizing inter-data switching activities

Abstract

The switching activity of a computation unit is the major reason behind power dissipation. In this work, the digital signal processor (DSP) core is developed by minimizing switching activities of its functional blocks based on dynamic ranges of input data. To achieve low-power dissipation, it employs the Booth-algorithm multiplier encoding one of two input data with a smaller dynamic range, and the adder operating at a larger dynamic range of two input data. When dynamic ranges of input data do not expand the entire word length. the power dissipation of the proposed DSP core can be reduced by decreasing the number of switching activities. According to the HSPICE circuit simulation using the TSMC 0.35 /spl mu/m CMOS technology, the proposed DSP core operating at 100 MHz has less power dissipation than that of the conventional one when performing addition, multiplication and multiplication-accumulation operations. In addition, our DSP core would save 17.9% and 21.0% of power dissipation of the conventional one for performing the ITU G722 audio coder and discrete cosine transform of the JPEG image coder, respectively.