Abstract
The key challenge the SoC designers vanquish is on performance and energy consumption. Concerning this, the network on chip (NoC) evolved to accommodate greater numbers of IP cores on a die and empowering conventional technology. Intensive research has been going on globally keeping the major parameters in mind the latency, power consumption, bandwidth, and interconnect routing problems of conventional NoCs. Wireless network on chip (WiNoC) with on-chip antennas, routers, and transceivers is a promising trend in NoC in enhancing the performance and energy in multicore processors. This paper presents the survey on different architectures, tools, and technique which are used for state-of-the-art WiNoC. Researchers have designed and proposed several architectures and algorithms for different wireless hubs, traffic scenarios, and data injection rates with diverse IP cores which yield significantly improved results in terms of throughput, latency, and reliability.
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