Comprehensive majority/minority logic synthesis method

Abstract

New technologies such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET) and Tunneling Phase Logic (TPL) have been proposed as alternatives for CMOS technology. These technologies are based on the use of majority/minority logic. Existing logic synthesis methods targeting majority/minority logic based on three-feasible networks often result in non-optimal solutions. In this paper, we propose an improved synthesis technique that can process three-feasible and four-feasible networks. A method for finding the minimal majority expressions for all functions with four or fewer variables is given and a comprehensive synthesis method is provided. For the 21 Microelectronics Center of North Carolina (MCNC) benchmarks presented in this paper, the proposed approach yields an average reduction of 9.6% in the number of gate counts and 7.6% in the number of levels when compared with the best existing method.