Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies

Abstract

Due to the physical limitation of CMOS technology researchers are actively exploring other alternatives such as Quantum dot cellular automata (QCA), Nano magnetic logic (NML), Single electron tunneling (SET) and Tunneling phase logic (TPL). These emerging technologies utilize majority gate as a base component for synthesis of logic network. This paper presents a novel heuristic based majority logic synthesis (HMLS) which reduces the time complexity of the synthesis process, and also overcomes the scalability problem faced by currently available synthesis algorithms based on k-map technique. In addition, an updated library is proposed for majority logic synthesis based on 3-input and 5-input majority gates for further optimization of synthesis process. Experiments on microelectronics center of north Carolina (MCNC) benchmarks indicate that, the proposed approach has achieved an average reduction of 33% in majority level and an average reduction of 38% in gate count. Furthermore, while performing experiment for QCA as test case, the proposed approach has achieved an average reduction of 33% in circuit delay and an average reduction of 4% in circuit area.