Comprehensive Analysis of Quantum Mechanical Effects of Interface Trap and Border Trap Densities of High-k Al2O3/In0.53Ga0.47As on a 300-mm Si Substrate

Walid Amir,Tae-Woo Kim,Dae-Hyun Kim

doi:10.1109/access.2020.3038856

Walid Amir, Tae-Woo Kim + Show 1 more

Open Access

https://doi.org/10.1109/access.2020.3038856

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Abstract

We investigated the effects of quantum confinement in determining the interface traps (Dit) and border traps (Nbt) of ALD deposited Al2O3 with temperature variations onto InxGa1-xAs on a 300-mm Si (001) substrate. We also analysed the impact of these effects on the total gate capacitance of high- $k$ /Si and high- $k$ /InxGa1-xAs structures using 1D Poisson-Schrodinger solver simulation tool (Nextnano). While quantum confinement has no or very little impact on the gate capacitance of high- $k$ /Si structure, it has a considerably high amount of impact on the high- $k$ /InxGa1-xAs structures and substantially lowers the total gate capacitance. To reflect the actual thickness between the insulator-semiconductor interface and charge centroid, capacitance-equivalent-thickness was used to reflect the effects of quantum confinement in the InxGa1-xAs layer. The Dit and Nbt values extracted using capacitance-equivalent-thickness were observed to be around 10% and 25%, respectively, higher than the values of extraction with equivalent-oxide-thickness.

Highlights

III-V materials such as InxGa1-xAs have higher electron velocities, which result in considerably better electron transport properties compared to Si[5], [11]. This high electron mobility can contribute to high on-state current and faster switching speed. This high electron mobility originates from the low effective mass of III-V channel material, which contributes to the lower density of states (DOS) to the channel layer[12]–[14]
In this study, we attempted to show the impact of quantum mechanical confinement on interface trap density (Dit) as well as border traps (Nbt) for scaled down III-V metal oxide semiconductor devices
We found that inversion-layer capacitance is much larger compared to insulator capacitance in Si structure, having no or very low impact on total gate capacitance

Summary

INTRODUCTION

Traditional Si/SiO2 metal-oxide-semiconductor devices have reached the peak limit of scalability. This high electron mobility originates from the low effective mass of III-V channel material, which contributes to the lower density of states (DOS) to the channel layer[12]–[14] Because of this low DOS, the strong inversion Fermi level (EF) moves inside the conduction band (EC)[15]. GATE CAPACITANCE MODEL The total gate capacitance of InxGa1-xAs MOS devices can be represented as a series combination of two capacitances known as insulator capacitance (Cins) and inversion-layer capacitance (Cinv) (Figure 2a), considering that beneath the channel, there is no doping level. Qi is the total electron charge of the sub-band i located at the channel, the energy level of the sub-band i is Ei , and m||* denotes as the in-plane effective mass of the channel material, which can be calculated from the following equation[39]: m* = m* (1+ E) = 2k 2. Cacc is the measured accumulation capacitance of the MOS capacitors

DISCUSSION

E2 E3 E4 E5 E6 E7 E8 E9 E10 EF

CONCLUSION

Findings

Lin et al, “Enabling the high-performance InGaAs/Ge