Analytical capacitance modeling of multifin trapezoidal FinFET

Abstract

Triple-gate FinFETs have made rapid developments in the field of nanoelectronics industry due to their high immunity to short-channel effects, improved subthreshold swing, and channel mobility, etc. leading to improved speed and reduced power consumption. However, high parasitic capacitances at the gate limit their computational speed and analog/RF performances. This paper presents an analytical approach to modeling the parasitic capacitances of multigate multifin trapezoidal FinFETs. The total extrinsic gate capacitance is estimated taking into account the impact of external and internal fringing capacitances and overlap capacitances from gate to source/drain electrodes. The increase or decrease of extrinsic gate capacitance due to process parameters variation has been analyzed. It is found that the fin spacing exerts a crucial impact on total gate capacitance. The analysis reveals that reduction in fin spacing results in lower parasitic capacitances leading to better computational efficiency.