Abstract
A complex ±1 multiplier is an integral element in modern CDMA communication systems, specifically as a pseudonoise code scrambler/descrambler. An efficient implementation is essential to reduce the critical path delay, power, and area of wireless receivers. A signed-binary architecture is proposed to achieve this complex multiplier function. Tradeoffs and design solutions are discussed. It is shown that the VLSI circuit implementation of the arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. An analytical framework is developed that expands the scope of the functions that can be efficiently implemented using signed-binary representation. Simulations exhibit a significant speed improvement as compared to alternative architectures.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
