Complementary DMOS process for LSI

Abstract

This paper describes a new complementary metal-oxide semiconductor (CMOS) integrated circuit technology that utilizes a symmetrical double-diffused n-channel transistor. The features of the technology are the use of five masks, a self-aligned p-well diffusion and short channel n-MOS transistors. This results in a fifty percent reduction in p-well area as compared to conventional CMOS devices and lowers processing costs. Integrated circuits, fabricated using boron implantation for the p-well dose and p/SUP +/ diffusion, and arsenic implantation for the n/SUP +/ diffusion, exhibit a p-channel threshold of -1.8 V and an n-channel threshold of 1.2 V. The n-channel threshold is controlled by an initial boron implant of 3/spl times/10/SUP 14/ cm/SUP -2/ and subsequent double-diffusion steps. An invertor chain of seven cells bas been operated with a supply of 3-11 V. In operation, the delay per stage was 13 ns at 5 V and 5 ns at 10 V.