Compatible FPGA implementation of capacitor voltage balance control for half-bridge and full-bridge modular multilevel converter

Abstract

Industrial modular multilevel converter (MMC) controllers usually implement the sub-module (SM) capacitor voltage balance control (VBC) in field-programmable gate array (FPGA) boards. Conventional VBC methods need to sort out the capacitor voltages, where the sorting algorithm would become too complex to be accommodated in FPGA if the SM number is large. A sorting-less VBC optimized for FPGA implementation is proposed and validated for half-bridge MMC in previous works. This paper continues the work and proposes a compatible VBC FPGA implementation for both half-bridge and full-bridge topologies. The proposed VBC is implemented in an FPGA based real time simulator and investigated in a full-bridge MMC STATCOM test system. The VBC for large MMC (1024 SM per valve) can be implemented in one Virtex 7 FGPA board with an execution cycle time of 250 nanoseconds. The performance is validated in steady states, transients, and fault conditions.