Abstract

This paper investigate instability in device characteristics related to the hot carrier effect, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature (PBTI) under DC stress for n- and p-channel thin-film Silicon on Insulator (SOI) power MOSFET at high temperature. The threshold voltage shift increases as the temperature rises due to PBTI for n-MOSFET and NBTI for p-MOSFET. Drain Avalanche Hot Carrier (DAHC) occurs when the gate stress voltage is near the threshold voltage and Channel Hot Carrier (CHC) occurs when the gate voltage is high. The threshold voltage shift and the degradation rate of on-resistance of the n-MOSFET is larger than that of the p-MOSFET due to the difference in the impact ionization coefficient between electrons and holes.

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