Abstract
This paper introduces two efficient computational techniques for Orthogonal Frequency Division Multiplexing (OFDM) based transmitter design with interpolation filters and discusses the corresponding VLSI architecture issues. The proposed technique is demonstrated by detailing the implementation of a 64-point, radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> SDF FFT in combination with digital interpolation filters. By exploiting the redundancy into the cyclic prefix part of the OFDM symbol, the computational load of the transmitter is reduced by approximately 20% for the IEEE 802.11 WLAN standard. The first technique outperforms the second one regarding the number of operations, while the second one is more appealing for applications where required area is an issue.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
