Abstract
This paper introduces an efficient computational technique for Orthogonal Frequency Division Multiplexing (OFDM) design with digital pulse shaping filters and discusses the corresponding VLSI architecture issues. In the proposed architecture a 64-point, radix-4 pipelined FFT is implemented in combination with a parallel digital pulse shaping filter architecture. By exploiting the redundancy in to the cyclic prefix part of the OFDM symbol, a significant 20% reduction of the required arithmetic operations is accomplished.
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