Comparison of two PwWM schemes for SiC-device-based split output converters in high-switching-frequency applications

Abstract

The adoption of the fast-switching silicon carbide (SiC) devices in the conventional two-level voltage source converters can bring issues such as crosstalk effect, high turnon losses, electromagnetic interference (EMI), etc. The split output converter can decouple the upper SiC MOSFET from the lower SiC MOSFET in the same phase leg with suppressed crosstalk effect, lower turn-on losses, and reduced EMI. These advantages enable the split output converter to operate at high switching frequencies (e.g. 100kHz). However, as a limiting factor at high switching frequencies, the dead time in the conventional pulse width modulation with synchronous rectification (SRPWM) can cause lowfrequency voltage/current harmonics, reduce the linear modulation region, and lower the dc-link voltage utilization. In contrast, the current direction related pulse width modulation (CDPWM) has no such problems due to the abandon of the dead time. A detailed comparison between the SRPWM and the CDPWM is carried out in this paper regarding harmonics, control, and efficiency. Both the analysis and the experimental results verify that, the CDPWM is superior to the SRPWM for the SiC-device-based split output converters in high-switching-frequency applications.