Comparison of the SET sensitivity of standard logic gates designed in 130 nm CMOS technology

Abstract

This paper analyzes the sensitivity of five standard logic gates (AND, OR, INV, NAND and NOR) to Single Event Transients (SETs). All gates have been designed in IHP's 130 nm bulk CMOS technology. The analysis was conducted with SPICE simulations, employing the current injection concept to model the SET effects. The SET sensitivity of the investigated logic gates was evaluated in terms of critical charge. For each logic gate, the dependence of the critical charge on the input logic levels, size of target gate and size of load gate was investigated. Obtained results have shown that it is possible to establish a simple linear model for estimating the critical charge as a function of the sizing factors of target and load gates, for all investigated logic gates and all combinations of input logic levels. The model provides very good accuracy compared to the results obtained by SPICE simulations. Integrating the proposed model into a high-level SET evaluation tool would allow to reduce the number of required circuit-level simulations for evaluating the SET robustness of complex digital circuits composed of standard logic gates.