Comparison of RL and LC Output Matching Networks for Cascode Inductive Source Degeneration LNA in 45 nm CMOS Technology

Abstract

This paper reports the designing of low noise amplifier (LNA) using the inductive source degeneration with cascode topology with different output matching stages namely resistive with inductive load (RL circuit) and inductive with capacitive load (LC circuit) in 45 nm CMOS process technology at 2.4GHz frequency. The implementation was done in Advanced Design System (ADS) software. The LNA obtained moderate gain of 5.046 dB, input reflection coefficient of -10.869 dB, maximum gain of 15.410 dB, and noise figure of 3.590 dB and with power consumption of 8mW for RL output matching network at 2.4GHz ISM band. For LC matching network, the LNA achieves high linearity 21.597 dB, high gain of 18.408 dB with low power consumption 2 mW, respectively.