A high gain low noise amplifier design & comparative analysis with other MOS-topologies for Bluetooth applications at 130nm CMOS

Abstract

The design procedure with the optimum performance of a Low Noise Amplifier (LNA) is presented. The noise performance, Linearity, power dissipation and high gain feature of an LNA have been qualitatively analyzed and finally an optimum LNA design topology has been tried to achieve, among possible common source (C-S) architectures with 0.13μm CMOS process. The design has been targeted on the Bluetooth application range (2.4GHz-2.6GHz), due to its wide usage and popularity with the supply ranging in 1.5/2.5V. Basic Common-source LNA with inductive source degeneration, Cascode-LNA and Cascode-LNA with C-S stage have been designed and compared for the optimum results for Linearity, gain, noise and power. The development of all three LNA topologies have lead to provide the noise figure of 1.25dB with a forward gain of 33dB and a very low power consumption with two stage cascoded common source LNA topology. The LNA is designed and simulated on Advanced Design System (ADS) from Agilent with UMC 0.13μm RF CMOS process.