Comparison of nano-scale complementary metal-oxide semiconductor and 3T–4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic

Abstract

Subthreshold logic has gained wide research interest due to their suitability for ultra low-power applications, such as radio frequency identification, wireless micro sensors and so on, which demand low-energy consumption. Important concerns for subthreshold logic at present are increased sensitivity to process, voltage and temperature (PVT) variations. Analysis is done addressing the nano-scale complementary metal-oxide semiconductor (CMOS) device and circuit subthreshold behaviour to PVT variations, showing their poor performance and robustness in terms of power, delay, energy consumption and so on. Next part of the study addresses how double gate (DG) fin-shaped field-effect transistors (FinFETs) are better candidates for subthreshold logic in comparison to equivalent bulk CMOS devices in terms of robustness. It is observed that DGFinFETs have almost 81% better power performance characteristics than equivalent bulk CMOS option for subthreshold operation. Among the various DGFinFET device options, 3TDG (tied gate DG) device option has better (approximately 77%) energy delay product (EDP) characteristics than 4TDG (independent gate DG) device option for subthreshold operation. Comparative studies show the suitability of symmetric, asymmetric oxide features in combination with tied and independent gate options for subthreshold operation, showing better EDP characteristics of 3TSDG device option and better robustness of 4TSDG device option.