Comparison of gate geometries for tunable, local barriers in InAs nanowires

Abstract

We report measurements and analysis of gate-induced electrostatic barriers for electron transport in InAs nanowires. Three types of local gates are analyzed; narrow gates (50−100 nm) located on top of or below the nanowire, and wide gates overlapping the interfaces between nanowire and source and drain electrodes. We find that applying negative potentials to the local gate electrodes induces tunable barriers of up to 0.25 eV and that transport through the wire can be blocked at neutral and slightly positive potentials on the nanowire-contact gates, indicating that built-in barriers can exist at the nanowire-contact interface. The contact gates can be biased to remove the unwanted interface barriers occasionally formed during processing. From the temperature dependence of the conductance, the barrier height is extracted and mapped as a function of gate voltage. Top and bottom gates are similar to each other in terms of electrostatic couplings (lever arms ∼0.1−0.2 eV/ V) and threshold voltages for barrier induction (Vg∼−1 to −2 V), but low temperature gate sweeps suggest that device stability could be affected by the differences in device processing for the two gate geometries.