Comparison of 0.25 μm bulk, PD and FD SOI CMOS implementations of a low-voltage low-power programmable DLL for linear delay generation

Abstract

This paper describes the SOI implementation of a low-voltage low-power programmable delay locked loop (DLL) for linear delay generation in graphics display applications. In order to achieve the best linearity performance, a new scale structure with programmable delay stages is introduced. Since a programmable stage increases the complexity and thus the minimum achievable delay, a high performance technology is required to implement the target specifications. Simulation results in 0.25 /spl mu/m bulk, partially-depleted (PD) and fully-depleted (FD) SOI CMOS are compared and experimental results are reported for the most promising FD process.