Comparison between bipolar and NMOS transistors in linearization technique at 5GHz low noise amplifier

Abstract

This paper presents a comparison between bipolar and NMOS transistor to get high linearity amplifier. Using bipolar transistor, the amplifier has high linearity, and it does not sensitive to component variations. High linear amplifier using bipolar transistor has been designed and was fabricated using TSMC 0.18 um CMOS 1P6M process. The high linearity amplifier exhibits measurements results as 10.5 dB gain, noise figure less than 2.1 dB, input return loss is less than -15.9 dB, output return loss less than -15.8 dB, input third order intercept point is more than 16 dBm, and 7.6 mW of power consumption at 5 GHz.