Comparator‐noise‐based residue measurement and correction technique in 16 bit 1 MS/s SAR ADC

Abstract

AbstractThis letter presents an accuracy enhancement technique utilized in 16 bit fully differential successive‐approximation‐register analog‐to‐digital converters (SAR ADC). For noise performance improvement to obtain a higher ENOB, the residue measurement technique which statistically estimates the input residual error of comparator with Gaussian noise fitting is presented. The ADC digital output is compensated by the residue measurement results. It is verified in the 0.18‐μm 1P5M 5 V CMOS process. Finally, a 93.1 dB SNR and a 110.5 dB SFDR are measured operating at 1 MS/s with a 10‐kHz input tone and larger than 1‐dB SNR improvement is obtained in different chips.