Abstract
This paper presents a 12bit 100Ms/s fully-self timed SAR ADC. A timer circuit is introduced in order to self-time the sub-ADC settlement. Redundancy and monotonic switching techniques are adopted to further enhance the conversion speed. A source follower based high speed reference buffer is included on the chip. To adaptively adjust the drive strength under different PVT condition, a bias current adjustment feedback loop is designed. The proposed SAR ADC is designed with 55nm CMOS process, the active core circuit occupies an area of 560μm*320μm. The simulated result indicates that 75.2dB SFDR, 70.7dB SNR, 69dB SNDR are achieved.
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