Abstract
This paper presents hardware and bit-error-rate (BER) performance analysis of simplified maximum-a-posteriori (MAP) algorithms based on piece-wise-linear-approximations and Maclaurin-series-expansion for the turbo codes. From this comparative study, a simplified MAP algorithm with optimal BER performance is selected and an architecture suitable for high speed application is suggested for the design of soft-input-soft-output (SISO) unit. Subsequently, a quantitative model is proposed for estimating the amount of memory required by SISO unit in terms of sliding window size, data width of internal metrics and total number of systematic and parity bits. Thereafter, a non-parallel-radix-2 architecture of turbo decoder which incorporates SISO unit and quadratic-permutation-polynomial interleaver is presented. Application-specific-integrated-circuit (ASIC) implementation of this turbo decoder is carried out in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology node and its power consumption, design area and operating clock frequency are reported. Finally, a comparison with similar contributions in the literature has shown that the implemented turbo decoder achieves energy efficiency of 0.28 nJ/b/iteraions. Similarly, it has achieved a highest throughput of 28 Mbps among radix-2 and radix-4 non-parallel turbo decoders.
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